As semiconductor devices have become highly integrated, the sizes of active regions and field regions on semiconductor substrates have been reduced. Various conductive structures can be formed in an active region and electrically separated from one another by a field region having an insulation layer. A field region is conventionally referred to as an isolation region and the insulation layer in the field region is conventionally referred to as an isolation layer. Conductive structures are frequently referred to as a conductive device, so the isolation region and the isolation layer are also referred to as a device isolation region and a device isolation layer, respectively. The reduction of size of an active region may cause a reduction of a gate length in a metal oxide semiconductor field effect transistor (MOSFET).
Particularly, the reduction of a gate length in a p-channel MOSFET (hereinafter referred to as p-MOSFET) may generate a parasitic transistor at a boundary portion between the active region and the device isolation region of a substrate due to a short channel length of the p-MOSFET. “Hot electrons induced punchthrough” (HEIP) may be discharged from the gate to thereby deteriorate the characteristics of the p-MOSFET.
Conventionally, a dummy pattern, such as a tab, may be formed on the boundary area between the active region and the device isolation region during the formation of a conventional gate of a p-MOSFET, so that the gate has a length sufficient to minimize HEIP.
However, the above conventional method of reducing HEIP may have various problems: Firstly, the dummy pattern may not contribute the elongation of the gate length when the gate is not aligned with the active region. Secondly, when neighboring gates are not spaced apart from each other by a sufficient distance, the dummy pattern may not be formed into a sufficient size. As a result, the dummy pattern may not contribute to the elongation of the gate length. For example, there may be a problem that neighboring dummy patterns are connected to each other when the gate has a length below about 90 nm. Thirdly, the channel length may be difficult to control at the boundary portion of the active region and the device isolation region due to a rounding effect.